diff options
author | whitequark <whitequark@whitequark.org> | 2019-07-09 08:14:52 +0000 |
---|---|---|
committer | whitequark <whitequark@whitequark.org> | 2019-07-09 09:30:58 +0000 |
commit | 44bcb7a187ffa00921cb14fa50428ce272ce3b6b (patch) | |
tree | b9f0636001c8fb2464afdbcc5521fc07d0ea5ff0 /passes/proc/proc_init.cc | |
parent | 5fe0ffe30f315d50b2405c2d436ad8e7ca9ba2f6 (diff) | |
download | yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.tar.gz yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.tar.bz2 yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.zip |
proc_prune: promote assigns to module connections when legal.
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
Diffstat (limited to 'passes/proc/proc_init.cc')
-rw-r--r-- | passes/proc/proc_init.cc | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index e2dc07e53..462a384b7 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -26,21 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) -{ - log_assert(rule.compare.size() == 0); - - while (1) { - RTLIL::SigSpec tmp = sig; - for (auto &it : rule.actions) - tmp.replace(it.first, it.second); - if (tmp == sig) - break; - sig = tmp; - } -} - -void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) +void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) { bool found_init = false; @@ -53,9 +39,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) for (auto &action : sync->actions) { RTLIL::SigSpec lhs = action.first; - RTLIL::SigSpec rhs = action.second; - - proc_get_const(rhs, proc->root_case); + RTLIL::SigSpec rhs = sigmap(action.second); if (!rhs.is_fully_const()) log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs)); @@ -120,10 +104,12 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); for (auto mod : design->modules()) - if (design->selected(mod)) + if (design->selected(mod)) { + SigMap sigmap(mod); for (auto &proc_it : mod->processes) if (design->selected(mod, proc_it.second)) - proc_init(mod, proc_it.second); + proc_init(mod, sigmap, proc_it.second); + } } } ProcInitPass; |