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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 00:21:46 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-08 20:16:29 +0100 |
| commit | 4e03865d5bf3fafe0bd3735c88431675d53d2663 (patch) | |
| tree | 7ef637bd0526b498d32386bc1c79c671a02af7f0 /passes/proc/proc_init.cc | |
| parent | c00a29296c8d3446c7cfe253080c7e33358219b0 (diff) | |
| download | yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.gz yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.bz2 yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.zip | |
Add support for memory writes in processes.
Diffstat (limited to 'passes/proc/proc_init.cc')
| -rw-r--r-- | passes/proc/proc_init.cc | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index eb323038d..b705251dd 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -71,17 +71,8 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) offset += lhs_c.width; } } + sync->actions.clear(); } - - if (found_init) { - std::vector<RTLIL::SyncRule*> new_syncs; - for (auto &sync : proc->syncs) - if (sync->type == RTLIL::SyncType::STi) - delete sync; - else - new_syncs.push_back(sync); - proc->syncs.swap(new_syncs); - } } struct ProcInitPass : public Pass { |