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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:08:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 11:27:48 +0200 |
| commit | 7bd2d1064f2eceddc3c93c121c4154a2f594a040 (patch) | |
| tree | 563de1df5e323d0f217a51e29acb56c9e9f1327d /passes/proc/proc_init.cc | |
| parent | d86a25f145012ccb6b2048af3aae22f13b97b505 (diff) | |
| download | yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.gz yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.tar.bz2 yosys-7bd2d1064f2eceddc3c93c121c4154a2f594a040.zip | |
Using log_assert() instead of assert()
Diffstat (limited to 'passes/proc/proc_init.cc')
| -rw-r--r-- | passes/proc/proc_init.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 99498505f..c72840c02 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -25,7 +25,7 @@ static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule) { - assert(rule.compare.size() == 0); + log_assert(rule.compare.size() == 0); while (1) { RTLIL::SigSpec tmp = sig; |