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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 22:54:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 22:54:39 +0200 |
| commit | 65a939cb2767623b95adcd2ec5e783b828c1f9eb (patch) | |
| tree | a9b397c0a545d82278d7635d519899ab1bc0768d /passes/proc/proc_mux.cc | |
| parent | f80da7b41dd9c12d3bd65ceab6c0c6748a70a78c (diff) | |
| download | yosys-65a939cb2767623b95adcd2ec5e783b828c1f9eb.tar.gz yosys-65a939cb2767623b95adcd2ec5e783b828c1f9eb.tar.bz2 yosys-65a939cb2767623b95adcd2ec5e783b828c1f9eb.zip | |
Fixed memory corruption with new SigSpec API in proc_mux
Diffstat (limited to 'passes/proc/proc_mux.cc')
| -rw-r--r-- | passes/proc/proc_mux.cc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index cd459d949..50ba8fa1e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -68,20 +68,16 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, for (auto comp : compare) { RTLIL::SigSpec sig = signal; - sig.expand(); - comp.expand(); // get rid of don't-care bits assert(sig.size() == comp.size()); for (int i = 0; i < comp.size(); i++) - if (comp.chunks()[i].wire == NULL && comp.chunks()[i].data.bits[0] == RTLIL::State::Sa) { - sig.remove(i, 1); - comp.remove(i--, 1); + if (comp[i] == RTLIL::State::Sa) { + sig.remove(i); + comp.remove(i--); } if (comp.size() == 0) return RTLIL::SigSpec(); - sig.optimize(); - comp.optimize(); if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1)) { |