Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx

1 files changed, 18 insertions, 11 deletions

diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index 9e00b0a8a..d4aee9df0 100644
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -65,8 +65,7 @@ struct PruneWorker
 			pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected);
 			assigned.insert(sw_assigned.begin(), sw_assigned.end());
 		}
-		pool<RTLIL::SigSig> remove;
-		for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) {
+		for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) {
 			RTLIL::SigSpec lhs = sigmap(it->first);
 			bool redundant = true;
 			for (auto &bit : lhs) {
@@ -75,22 +74,32 @@ struct PruneWorker
 					break;
 				}
 			}
+			bool remove = false;
 			if (redundant) {
 				removed_count++;
-				remove.insert(*it);
+				remove = true;
 			} else {
 				if (root) {
 					bool promotable = true;
 					for (auto &bit : lhs) {
-						if (bit.wire && affected[bit]) {
+						if (bit.wire && affected[bit] && !assigned[bit]) {
 							promotable = false;
 							break;
 						}
 					}
 					if (promotable) {
+						RTLIL::SigSpec rhs = sigmap(it->second);
+						RTLIL::SigSig conn;
+						for (int i = 0; i < GetSize(lhs); i++) {
+							RTLIL::SigBit lhs_bit = lhs[i];
+							if (lhs_bit.wire && !assigned[lhs_bit]) {
+								conn.first.append_bit(lhs_bit);
+								conn.second.append(rhs.extract(i));
+							}
+						}
 						promoted_count++;
-						module->connect(*it);
-						remove.insert(*it);
+						module->connect(conn);
+						remove = true;
 					}
 				}
 				for (auto &bit : lhs)
@@ -100,11 +109,9 @@ struct PruneWorker
 					if (bit.wire)
 						affected.insert(bit);
 			}
-		}
-		for (auto it = cs->actions.begin(); it != cs->actions.end(); ) {
-			if (remove[*it]) {
-				it = cs->actions.erase(it);
-			} else it++;
+			if (remove)
+				cs->actions.erase((it++).base() - 1);
+			else it++;
 		}
 		return assigned;
 	}