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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:30:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 16:30:53 -0700 |
| commit | d880f73c79d897107a54f7734c2a1dea302c930c (patch) | |
| tree | d4fbb25c6b59707ecb6645672c9f336e142da0c9 /passes/proc/proc_rmdead.cc | |
| parent | 2217d59e299ce0cc15887d53308d7b7cb6400c52 (diff) | |
| parent | db1a5ec6a2a437b296e7ba9de78afaf3b440327f (diff) | |
| download | yosys-d880f73c79d897107a54f7734c2a1dea302c930c.tar.gz yosys-d880f73c79d897107a54f7734c2a1dea302c930c.tar.bz2 yosys-d880f73c79d897107a54f7734c2a1dea302c930c.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/proc/proc_rmdead.cc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 7c334e661..d2f8d9ead 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |