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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:20:15 +0100 |
| commit | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (patch) | |
| tree | 92071580c9bd60888ee5861d59457947a8adfde7 /passes/proc | |
| parent | ecc30255ba70910777a4586f5bd6abc818073293 (diff) | |
| download | yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.gz yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.tar.bz2 yosys-369bf81a7049c96f62af084bb5007fbf45e36ab4.zip | |
Added support for non-const === and !== (for miter circuits)
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 65dc97bdd..571946573 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -47,7 +47,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp polarity = !polarity; return check_signal(mod, cell->connections["\\A"], ref, polarity); } - if (cell->type == "$eq" && cell->connections["\\Y"] == signal) { + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) { if (cell->connections["\\A"].is_fully_const()) { if (!cell->connections["\\A"].as_bool()) polarity = !polarity; @@ -59,7 +59,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp return check_signal(mod, cell->connections["\\A"], ref, polarity); } } - if (cell->type == "$ne" && cell->connections["\\Y"] == signal) { + if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) { if (cell->connections["\\A"].is_fully_const()) { if (cell->connections["\\A"].as_bool()) polarity = !polarity; |