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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 11:58:25 +0200 |
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| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 11:58:25 +0200 |
| commit | 397dfccb304a12a40d34c4454a5cb4acee8be75f (patch) | |
| tree | 39f2bdcbfbc62de55f7333c0bcfb509735bf561a /passes/proc | |
| parent | d9a438101298710b9dadd4e7a1cb0041e8ba4199 (diff) | |
| download | yosys-397dfccb304a12a40d34c4454a5cb4acee8be75f.tar.gz yosys-397dfccb304a12a40d34c4454a5cb4acee8be75f.tar.bz2 yosys-397dfccb304a12a40d34c4454a5cb4acee8be75f.zip | |
Support for SystemVerilog interfaces as a port in the top level module + test case
Diffstat (limited to 'passes/proc')
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