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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-12 14:57:01 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-12 14:57:01 +0200 |
| commit | 48bc203653f10e0081f646f03c20f598f7420855 (patch) | |
| tree | 805b7ddc2ec354f091aa66d44e50c49be32f74f2 /passes/proc | |
| parent | 0deaccbaae436bc94ad5b2913fa39a9368c09ace (diff) | |
| parent | 7685469ee2f7bc038c4fd6fe98f93eb08d6fac7c (diff) | |
| download | yosys-48bc203653f10e0081f646f03c20f598f7420855.tar.gz yosys-48bc203653f10e0081f646f03c20f598f7420855.tar.bz2 yosys-48bc203653f10e0081f646f03c20f598f7420855.zip | |
Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 7c334e661..d2f8d9ead 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); + bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |