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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /passes/sat/assertpmux.cc | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'passes/sat/assertpmux.cc')
| -rw-r--r-- | passes/sat/assertpmux.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 3b432c461..b4adb1ab3 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -57,9 +57,9 @@ struct AssertpmuxWorker int width = cell->getParam("\\WIDTH").as_int(); int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1; - SigSpec sig_a = sigmap(cell->getPort("\\A")); - SigSpec sig_b = sigmap(cell->getPort("\\B")); - SigSpec sig_s = sigmap(cell->getPort("\\S")); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); for (int i = 0; i < numports; i++) { SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width); @@ -98,12 +98,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort("\\S")); + muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S)); else - muxport_actsignal[muxport] = cell->getPort("\\S")[portidx-1]; + muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort("\\Y")[bitidx]))); + output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx]))); } output.sort_and_unify(); @@ -151,7 +151,7 @@ struct AssertpmuxWorker int swidth = pmux->getParam("\\S_WIDTH").as_int(); int cntbits = ceil_log2(swidth+1); - SigSpec sel = pmux->getPort("\\S"); + SigSpec sel = pmux->getPort(ID::S); SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) @@ -164,7 +164,7 @@ struct AssertpmuxWorker assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); if (!flag_always) - assert_en.append(get_activation(pmux->getPort("\\Y"))); + assert_en.append(get_activation(pmux->getPort(ID::Y))); if (GetSize(assert_en) == 0) assert_en = State::S1; @@ -174,8 +174,8 @@ struct AssertpmuxWorker Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); - if (pmux->attributes.count("\\src") != 0) - assert_cell->attributes["\\src"] = pmux->attributes.at("\\src"); + if (pmux->attributes.count(ID::src) != 0) + assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src); } }; |