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authorSergey <37293587+SergeyDegtyar@users.noreply.github.com>2019-10-01 10:57:09 +0300
committerGitHub <noreply@github.com>2019-10-01 10:57:09 +0300
commitd99b1e32618f8aa92c01eb0ac5d08486f411cca0 (patch)
tree5671ffa605b5f6b31b86aacb2dbeaacd018302d7 /passes/sat/async2sync.cc
parentfc56459746fec7751735749e3328378e1089b914 (diff)
parentd963e8c2c6207ad98d48dc528922ad58c030173f (diff)
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Merge branch 'master' into SergeyDegtyar/anlogic
Diffstat (limited to 'passes/sat/async2sync.cc')
-rw-r--r--passes/sat/async2sync.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 24ae6e448..740248545 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -198,6 +198,7 @@ struct Async2syncPass : public Pass {
module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
}
+ cell->setPort("\\D", sig_q);
cell->setPort("\\Q", new_q);
cell->unsetPort("\\EN");
cell->unsetParam("\\EN_POLARITY");