FfData: some refactoring.

- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases

1 files changed, 18 insertions, 19 deletions

diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index d90206b46..a292941c8 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -153,6 +153,23 @@ struct Clk2fflogicPass : public Pass {
 						continue;
 					}
 
+					if (ff.has_clk) {
+						log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
+					} else if (ff.has_aload) {
+						log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
+					} else {
+						// $sr.
+						log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
+								log_id(module), log_id(cell), log_id(cell->type),
+								log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
+					}
+
+					ff.remove();
+
 					Wire *past_q = module->addWire(NEW_ID, ff.width);
 					if (!ff.is_fine) {
 						module->addFf(NEW_ID, ff.sig_q, past_q);
@@ -163,7 +180,7 @@ struct Clk2fflogicPass : public Pass {
 						initvals.set_init(past_q, ff.val_init);
 
 					if (ff.has_clk) {
-						ff.unmap_ce_srst(module);
+						ff.unmap_ce_srst();
 
 						Wire *past_clk = module->addWire(NEW_ID);
 						initvals.set_init(past_clk, ff.pol_clk ? State::S1 : State::S0);
@@ -173,10 +190,6 @@ struct Clk2fflogicPass : public Pass {
 						else
 							module->addFfGate(NEW_ID, ff.sig_clk, past_clk);
 
-						log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
-								log_id(module), log_id(cell), log_id(cell->type),
-								log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q));
-
 						SigSpec clock_edge_pattern;
 
 						if (ff.pol_clk) {
@@ -203,16 +216,6 @@ struct Clk2fflogicPass : public Pass {
 						else
 							qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
 					} else {
-						if (ff.has_aload) {
-							log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
-									log_id(module), log_id(cell), log_id(cell->type),
-									log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q));
-						} else {
-							// $sr.
-							log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n",
-									log_id(module), log_id(cell), log_id(cell->type),
-									log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q));
-						}
 						qval = past_q;
 					}
 
@@ -246,10 +249,6 @@ struct Clk2fflogicPass : public Pass {
 					} else {
 						module->connect(ff.sig_q, qval);
 					}
-
-					initvals.remove_init(ff.sig_q);
-					module->remove(cell);
-					continue;
 				}
 			}
 		}