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| author | Jannis Harder <me@jix.one> | 2022-08-16 14:18:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-16 14:18:35 +0200 |
| commit | 556d008ed3c2db351e93e0075ccd47bdfb634fd9 (patch) | |
| tree | ab23fa7355df8f8ead24839ee7846e68cdbfb935 /passes/sat/clk2fflogic.cc | |
| parent | c26b2bf543a226e65a3fb07040bb278d668accf2 (diff) | |
| parent | f7023d06a2bda56467c8f07cc44d3b92f0eab2ba (diff) | |
| download | yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.gz yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.tar.bz2 yosys-556d008ed3c2db351e93e0075ccd47bdfb634fd9.zip | |
Merge pull request #3434 from jix/witness_flow
Updated formal flow with new witness format
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index b1b0567a0..2384ffced 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -233,7 +233,10 @@ struct Clk2fflogicPass : public Pass { qval = past_q; } - if (ff.has_aload) { + // The check for a constant sig_aload is also done by opt_dff, but when using verific and running + // clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids + // generating a lot of extra logic. + if (ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1)) { SigSpec sig_aload = wrap_async_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine, NEW_ID); if (!ff.is_fine) |