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| author | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
|---|---|---|
| committer | Archie <ac11018@ic.ac.uk> | 2022-08-21 17:18:20 -0500 |
| commit | db73f3c26b2768f93c7573b7c7d74b1cc7a0756d (patch) | |
| tree | 81696fd98770e519aea96fe3a6e40bcc3b3a4360 /passes/sat/clk2fflogic.cc | |
| parent | e7e8e3b0f65ea1ebfcf04bffd0d9ba90f8e0d7fe (diff) | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| download | yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.gz yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.tar.bz2 yosys-db73f3c26b2768f93c7573b7c7d74b1cc7a0756d.zip | |
Merge branch 'master' of https://github.com/ALGCDG/yosys
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index b1b0567a0..2384ffced 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -233,7 +233,10 @@ struct Clk2fflogicPass : public Pass { qval = past_q; } - if (ff.has_aload) { + // The check for a constant sig_aload is also done by opt_dff, but when using verific and running + // clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids + // generating a lot of extra logic. + if (ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1)) { SigSpec sig_aload = wrap_async_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine, NEW_ID); if (!ff.is_fine) |