Merge automatic and manual code changes for new cell connections API

1 files changed, 34 insertions, 34 deletions

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 22b724d53..a84faf792 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -83,8 +83,8 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
 	SigPool dffsignals;
 
 	for (auto &it : module->cells) {
-		if (ct.cell_known(it.second->type) && it.second->connections_.count("\\Q"))
-			dffsignals.add(sigmap(it.second->connections_.at("\\Q")));
+		if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q"))
+			dffsignals.add(sigmap(it.second->get("\\Q")));
 	}
 
 	for (auto &it : module->wires) {
@@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		info.cell = it.second;
 
 		if (info.cell->type == "$dff") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
 				bit_info[sig_q.at(i)] = info;
@@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$adff") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->connections_.at("\\ARST")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
 			info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
 			std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
@@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
 			info.clk_polarity = info.cell->type == "$_DFF_P_";
-			info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
+			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 
 		if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->connections_.at("\\R")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit();
 			info.clk_polarity = info.cell->type[6] == 'P';
 			info.arst_polarity = info.cell->type[7] == 'P';
 			info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-			info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
+			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 	}
@@ -514,11 +514,11 @@ struct ExposePass : public Pass {
 
 				for (auto &cell_name : info.cells) {
 					RTLIL::Cell *cell = module->cells.at(cell_name);
-					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->connections_.at("\\Q")).to_sigbit_vector();
+					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->connections_.at("\\Q") = cell_q_bits;
+					cell->set("\\Q", cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = new RTLIL::Wire;
@@ -536,7 +536,7 @@ struct ExposePass : public Pass {
 					connect_q.second.append(RTLIL::SigBit(wire_q, i));
 					set_q_bits.insert(wire_bits_vec[i]);
 				}
-				module->connections_.push_back(connect_q);
+				module->connect(connect_q);
 
 				RTLIL::Wire *wire_d = new RTLIL::Wire;
 				wire_d->name = wire->name + sep + "d";
@@ -544,7 +544,7 @@ struct ExposePass : public Pass {
 				wire_d->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
 				add_new_wire(module, wire_d);
-				module->connections_.push_back(RTLIL::SigSig(wire_d, info.sig_d));
+				module->connect(RTLIL::SigSig(wire_d, info.sig_d));
 
 				RTLIL::Wire *wire_c = new RTLIL::Wire;
 				wire_c->name = wire->name + sep + "c";
@@ -552,14 +552,14 @@ struct ExposePass : public Pass {
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
 				add_new_wire(module, wire_c);
 				if (info.clk_polarity) {
-					module->connections_.push_back(RTLIL::SigSig(wire_c, info.sig_clk));
+					module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
 					RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 					c->parameters["\\A_SIGNED"] = 0;
 					c->parameters["\\A_WIDTH"] = 1;
 					c->parameters["\\Y_WIDTH"] = 1;
-					c->connections_["\\A"] = info.sig_clk;
-					c->connections_["\\Y"] = wire_c;
+					c->set("\\A", info.sig_clk);
+					c->set("\\Y", wire_c);
 				}
 
 				if (info.sig_arst != RTLIL::State::Sm)
@@ -570,14 +570,14 @@ struct ExposePass : public Pass {
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
 					add_new_wire(module, wire_r);
 					if (info.arst_polarity) {
-						module->connections_.push_back(RTLIL::SigSig(wire_r, info.sig_arst));
+						module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
 						RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 						c->parameters["\\A_SIGNED"] = 0;
 						c->parameters["\\A_WIDTH"] = 1;
 						c->parameters["\\Y_WIDTH"] = 1;
-						c->connections_["\\A"] = info.sig_arst;
-						c->connections_["\\Y"] = wire_r;
+						c->set("\\A", info.sig_arst);
+						c->set("\\Y", wire_r);
 					}
 
 					RTLIL::Wire *wire_v = new RTLIL::Wire;
@@ -586,7 +586,7 @@ struct ExposePass : public Pass {
 					wire_v->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
 					add_new_wire(module, wire_v);
-					module->connections_.push_back(RTLIL::SigSig(wire_v, info.arst_value));
+					module->connect(RTLIL::SigSig(wire_v, info.arst_value));
 				}
 			}
 
@@ -628,18 +628,18 @@ struct ExposePass : public Pass {
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
 							RTLIL::SigSpec sig;
-							if (cell->connections_.count(p->name) != 0)
-								sig = cell->connections_.at(p->name);
+							if (cell->connections().count(p->name) != 0)
+								sig = cell->connections().at(p->name);
 							sig.extend(w->width);
 							if (w->port_input)
-								module->connections_.push_back(RTLIL::SigSig(sig, w));
+								module->connect(RTLIL::SigSig(sig, w));
 							else
-								module->connections_.push_back(RTLIL::SigSig(w, sig));
+								module->connect(RTLIL::SigSig(w, sig));
 						}
 					}
 					else
 					{
-						for (auto &it : cell->connections_)
+						for (auto &it : cell->connections())
 						{
 							RTLIL::Wire *w = new RTLIL::Wire;
 							w->name = cell->name + sep + RTLIL::unescape_id(it.first);
@@ -653,9 +653,9 @@ struct ExposePass : public Pass {
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
 							if (w->port_input)
-								module->connections_.push_back(RTLIL::SigSig(it.second, w));
+								module->connect(RTLIL::SigSig(it.second, w));
 							else
-								module->connections_.push_back(RTLIL::SigSig(w, it.second));
+								module->connect(RTLIL::SigSig(w, it.second));
 						}
 					}