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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
| commit | 956ecd48f71417b514c194a833a49238049e00b0 (patch) | |
| tree | 468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/sat/fminit.cc | |
| parent | 2d86563bb206748d6eef498eb27f7a004f20113d (diff) | |
| download | yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.gz yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.bz2 yosys-956ecd48f71417b514c194a833a49238049e00b0.zip | |
kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/sat/fminit.cc')
| -rw-r--r-- | passes/sat/fminit.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index f3f00b382..555a28dc6 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -147,7 +147,7 @@ struct FminitPass : public Pass { SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0; Wire *outwire = module->addWire(NEW_ID); - outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1; + outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1; if (clksig.empty()) module->addFf(NEW_ID, insig, outwire); @@ -161,7 +161,7 @@ struct FminitPass : public Pass { if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty()) { Wire *ffwire = module->addWire(NEW_ID); - ffwire->attributes[ID(init)] = State::S0; + ffwire->attributes[ID::init] = State::S0; SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]); if (clksig.empty()) |