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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 19:29:25 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 19:29:25 -0700 |
| commit | 2effa497a3328c75e88f4f70e9889428d2ee5524 (patch) | |
| tree | c0a7ab101b184d0f7aa4c33d2ce31eeb44271d05 /passes/sat/miter.cc | |
| parent | d6feb4b43e6082d3b3a240160086c02295b0af04 (diff) | |
| parent | 281a977b39ec832b5ad4d84027dc98a6e8f99d7c (diff) | |
| download | yosys-2effa497a3328c75e88f4f70e9889428d2ee5524.tar.gz yosys-2effa497a3328c75e88f4f70e9889428d2ee5524.tar.bz2 yosys-2effa497a3328c75e88f4f70e9889428d2ee5524.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/sat/miter.cc')
| -rw-r--r-- | passes/sat/miter.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 341a6bac8..9e150b60c 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -338,12 +338,12 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL else { Wire *assume_q = module->addWire(NEW_ID); - assume_q->attributes["\\init"] = State::S1; + assume_q->attributes["\\init"] = State::S0; assume_signals.append(assume_q); SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals); SigSpec assume_ok = module->Not(NEW_ID, assume_nok); - module->addFf(NEW_ID, assume_ok, assume_q); + module->addFf(NEW_ID, assume_nok, assume_q); SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals); module->addAnd(NEW_ID, assert_fail, assume_ok, trigger); |