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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
| commit | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (patch) | |
| tree | bcee5a22fc9ac7dca5b871ce667114e5f15d07d0 /passes/sat/miter.cc | |
| parent | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (diff) | |
| download | yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.gz yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.bz2 yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.zip | |
Added module->design and cell->module, wire->module pointers
Diffstat (limited to 'passes/sat/miter.cc')
| -rw-r--r-- | passes/sat/miter.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 0f00e71a6..ffd9f1b62 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; - design->modules_[miter_name] = miter_module; + design->add(miter_module); RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); |