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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:19:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:19:10 -0700 |
| commit | 8d820a9884c0a58ee7817a2052d8b915578a7ba7 (patch) | |
| tree | 7868bc0063dd0d36aa84a48c8ede1a3f3a8c37c3 /passes/sat/sat.cc | |
| parent | 3fa826254fb337e39334c8d94df6bcc142d17934 (diff) | |
| parent | fc727fa5c9e0a04a5dc1b4fcef652c5bca90b220 (diff) | |
| download | yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.tar.gz yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.tar.bz2 yosys-8d820a9884c0a58ee7817a2052d8b915578a7ba7.zip | |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'passes/sat/sat.cc')
| -rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,7 +268,7 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (!satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); |