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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:21:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 09:21:03 -0700 |
| commit | ba5d81c7f1d97ca09cefb0185b33e549e166cee2 (patch) | |
| tree | c70d709c9522c2b15891c40c1e265f5c2779465a /passes/sat/sat.cc | |
| parent | 9172d4a6740145e7b3c7c34b8fb5effd23598a94 (diff) | |
| parent | 13424352cc8dca5f08ad22aa42066dc7f62afea5 (diff) | |
| download | yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.tar.gz yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.tar.bz2 yosys-ba5d81c7f1d97ca09cefb0185b33e549e166cee2.zip | |
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Diffstat (limited to 'passes/sat/sat.cc')
| -rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index dd56d8c71..430bba1e8 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -268,7 +268,7 @@ struct SatHelper RTLIL::SigSpec removed_bits; for (int i = 0; i < lhs.size(); i++) { RTLIL::SigSpec bit = lhs.extract(i, 1); - if (!satgen.initial_state.check_all(bit)) { + if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) { removed_bits.append(bit); lhs.remove(i, 1); rhs.remove(i, 1); |