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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-07 15:00:14 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-07 15:00:14 +0100 |
| commit | 1b1ecd4ab0c3924d1acbaa0ccc22bd1933cb347c (patch) | |
| tree | 15687dd13061ae6156c63ffb831550acd38c1bd4 /passes/sat/sim.cc | |
| parent | b6aca1d7435ebd1cb37fe777a8b8d9564b859a50 (diff) | |
| download | yosys-1b1ecd4ab0c3924d1acbaa0ccc22bd1933cb347c.tar.gz yosys-1b1ecd4ab0c3924d1acbaa0ccc22bd1933cb347c.tar.bz2 yosys-1b1ecd4ab0c3924d1acbaa0ccc22bd1933cb347c.zip | |
Error checks for aiger witness
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index c669247e8..9771e83f3 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1099,6 +1099,8 @@ struct SimWorker : SimShared std::string type, symbol; int variable, index; dict<int, std::pair<SigBit,bool>> inputs, inits, latches; + if (mf.fail()) + log_cmd_error("Not able to read AIGER witness map file.\n"); while (mf >> type >> variable >> index >> symbol) { RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); Wire *w = topmod->wire(escaped_s); @@ -1410,9 +1412,14 @@ struct AIWWriter : public OutputWriter void write(std::map<int, bool> &) override { if (!aiwfile.is_open()) return; + if (worker->map_filename.empty()) + log_cmd_error("For AIGER witness file map parameter is mandatory.\n"); + std::ifstream mf(worker->map_filename); std::string type, symbol; int variable, index; + if (mf.fail()) + log_cmd_error("Not able to read AIGER witness map file.\n"); while (mf >> type >> variable >> index >> symbol) { RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); Wire *w = worker->top->module->wire(escaped_s); |