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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:04:05 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 12:04:05 +0200 |
| commit | 83cad82b295255d59e2162d599bbd4485b688c6a (patch) | |
| tree | bbc06736268f8c58f16808544d4b5b6ef7f1257c /passes/sat/sim.cc | |
| parent | c989adcc2d466bb3e2e83cf67ad0a193f6628fa6 (diff) | |
| download | yosys-83cad82b295255d59e2162d599bbd4485b688c6a.tar.gz yosys-83cad82b295255d59e2162d599bbd4485b688c6a.tar.bz2 yosys-83cad82b295255d59e2162d599bbd4485b688c6a.zip | |
latches are always set to zero
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 73e03067b..f480168bd 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1815,12 +1815,7 @@ struct AIWWriter : public OutputWriter for (int i = 0;; i++) { if (aiw_latches.count(i)) { - SigBit bit = aiw_latches.at(i).first; - auto v = current[mapping[bit.wire]].bits.at(bit.offset); - if (v == State::S1) - aiwfile << (aiw_latches.at(i).second ? '0' : '1'); - else - aiwfile << (aiw_latches.at(i).second ? '1' : '0'); + aiwfile << '0'; continue; } aiwfile << '\n'; |