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| author | Claire Wolf <clifford@clifford.at> | 2020-04-22 16:57:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-22 16:57:34 +0200 |
| commit | c32b4bded582e121056a497131bf617684448cc4 (patch) | |
| tree | 1ff19093149061387ee969ec2b898a7a0f2f4112 /passes/sat/sim.cc | |
| parent | 95c74b319b36f8cb950196c3e1d10c945629c1f5 (diff) | |
| parent | abf81c76396d674833d1dce3f3f75a43f76e2a1f (diff) | |
| download | yosys-c32b4bded582e121056a497131bf617684448cc4.tar.gz yosys-c32b4bded582e121056a497131bf617684448cc4.tar.bz2 yosys-c32b4bded582e121056a497131bf617684448cc4.zip | |
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
sim: Fix handling of constant-connected cell inputs at startup
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 59bf5a712..03ca42cf3 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -128,8 +128,12 @@ struct SimInstance for (auto &port : cell->connections()) { if (cell->input(port.first)) - for (auto bit : sigmap(port.second)) + for (auto bit : sigmap(port.second)) { upd_cells[bit].insert(cell); + // Make sure cell inputs connected to constants are updated in the first cycle + if (bit.wire == nullptr) + dirty_bits.insert(bit); + } } if (cell->type.in(ID($dff))) { |