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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:14:02 +0200 |
| commit | 3f4e3ca8ad480c2e73e2072ada77078ffd95e08f (patch) | |
| tree | 3117545be59991dc797086c5d273ed97220c75ef /passes/sat | |
| parent | 97a59851a6c411ccb06162d4b31725bf89262378 (diff) | |
| download | yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.tar.gz yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.tar.bz2 yosys-3f4e3ca8ad480c2e73e2072ada77078ffd95e08f.zip | |
More RTLIL::Cell API usage cleanups
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 198f83477..9ce3b43d3 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -629,7 +629,7 @@ struct ExposePass : public Pass { RTLIL::SigSpec sig; if (cell->has(p->name)) - sig = cell->connections().at(p->name); + sig = cell->get(p->name); sig.extend(w->width); if (w->port_input) module->connect(RTLIL::SigSig(sig, w)); |