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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 22:37:03 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-26 00:19:31 +0200 |
| commit | 64ba3c384255335d61e2d07160c57fa74156cde1 (patch) | |
| tree | 443a50c822682eaaf1475154948eefdea90e68f8 /passes/sat | |
| parent | d99fce3bc77a42563e1e270172e08ec25d58c7ab (diff) | |
| download | yosys-64ba3c384255335d61e2d07160c57fa74156cde1.tar.gz yosys-64ba3c384255335d61e2d07160c57fa74156cde1.tar.bz2 yosys-64ba3c384255335d61e2d07160c57fa74156cde1.zip | |
backends/verilog: Try to preserve mem write port priorities.
Diffstat (limited to 'passes/sat')
0 files changed, 0 insertions, 0 deletions