diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 09:51:17 +0100 |
| commit | edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487 (patch) | |
| tree | 602fc633af5de89d2d6d1bda480159318f4aa91d /passes/sat | |
| parent | 48ca1ff9ef5bba939348ceeec75ad310afd9fcf8 (diff) | |
| download | yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.gz yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.tar.bz2 yosys-edb3c9d0c4f0bc3a108ffebc01f02ff4d7354487.zip | |
Renamed extend() to extend_xx(), changed most users to extend_u0()
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/expose.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 46ebdb846..b012bc6a4 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -607,7 +607,7 @@ struct ExposePass : public Pass { RTLIL::SigSpec sig; if (cell->hasPort(p->name)) sig = cell->getPort(p->name); - sig.extend(w->width); + sig.extend_u0(w->width); if (w->port_input) module->connect(RTLIL::SigSig(sig, w)); else |