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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 20:36:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 20:36:48 -0700 |
| commit | 0157043b977e3b6715a6a568eb72aea247457eb0 (patch) | |
| tree | dea7eb229e23424e4ed3226c9c4e27f565c6b233 /passes/techmap/abc.cc | |
| parent | 802470746c320676d61431d420e33d34c239da84 (diff) | |
| parent | 9cb0456b6f9fa86240a747bab9780a28001b1a02 (diff) | |
| download | yosys-0157043b977e3b6715a6a568eb72aea247457eb0.tar.gz yosys-0157043b977e3b6715a6a568eb72aea247457eb0.tar.bz2 yosys-0157043b977e3b6715a6a568eb72aea247457eb0.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 15e79f9d1..65c7d1bb8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin continue; } } - - cell_stats[RTLIL::unescape_id(c->type)]++; + else + cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; |