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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-18 15:45:25 -0700 |
| commit | 42e40dbd0a513d430ff0a463f9a80dedfbbf51f5 (patch) | |
| tree | 5cf69498d43b8d225e28cf5562f91c3a4a94f814 /passes/techmap/abc.cc | |
| parent | 09411dd996f75dbce22a6f6979b7d61b0dae24f7 (diff) | |
| parent | e66e8fb59d8443c8d55c1185d6b2ce889a35357d (diff) | |
| download | yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.gz yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.tar.bz2 yosys-42e40dbd0a513d430ff0a463f9a80dedfbbf51f5.zip | |
Merge remote-tracking branch 'origin/master' into ice40dsp
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 15e79f9d1..65c7d1bb8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin continue; } } - - cell_stats[RTLIL::unescape_id(c->type)]++; + else + cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; |