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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:46:52 -0700 |
commit | 691e145cda416787fe214b5533c6ac3c8047bb65 (patch) | |
tree | ac78e40defe12c75bcc040f973217ad6875bf5af /passes/techmap/abc.cc | |
parent | 7eec64a38fb9362a43916aec79c7fca04b6ba72c (diff) | |
parent | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (diff) | |
download | yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.gz yosys-691e145cda416787fe214b5533c6ac3c8047bb65.tar.bz2 yosys-691e145cda416787fe214b5533c6ac3c8047bb65.zip |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'passes/techmap/abc.cc')
-rw-r--r-- | passes/techmap/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 5b19d84fb..15e79f9d1 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1453,7 +1453,7 @@ struct AbcPass : public Pass { log("internally. This is not going to \"run ABC on your design\". It will instead run\n"); log("ABC on logic snippets extracted from your design. You will not get any useful\n"); log("output when passing an ABC script that writes a file. Instead write your full\n"); - log("design as BLIF file with write_blif and the load that into ABC externally if\n"); + log("design as BLIF file with write_blif and then load that into ABC externally if\n"); log("you want to use ABC to convert your design into another format.\n"); log("\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); |