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| author | whitequark <whitequark@whitequark.org> | 2020-04-05 09:13:13 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-09 04:08:36 +0000 |
| commit | 711df56ad0174f5f437bcdb1939bc0153e2d051e (patch) | |
| tree | 1619478f5c55250ba305bce97f2c342af00bc7cc /passes/techmap/abc.cc | |
| parent | 9534b512770063baa48d862a375ec7a924766866 (diff) | |
| download | yosys-711df56ad0174f5f437bcdb1939bc0153e2d051e.tar.gz yosys-711df56ad0174f5f437bcdb1939bc0153e2d051e.tar.bz2 yosys-711df56ad0174f5f437bcdb1939bc0153e2d051e.zip | |
write_cxxrtl: add support for $sr cell.
Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
Diffstat (limited to 'passes/techmap/abc.cc')
0 files changed, 0 insertions, 0 deletions