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authorN. Engelhardt <nak@yosyshq.com>2022-08-25 11:41:12 +0200
committerGitHub <noreply@github.com>2022-08-25 11:41:12 +0200
commit8e640663d6b7ff84043068f48ed5f3cf7bff4321 (patch)
tree59001b194c2f573674c37352733427a3ec28a1c1 /passes/techmap/abc.cc
parent029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff)
parent9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 (diff)
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Merge pull request #3457 from KrystalDelusion/docs_width
Diffstat (limited to 'passes/techmap/abc.cc')
-rw-r--r--passes/techmap/abc.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 656c36b84..4039336dd 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1532,7 +1532,8 @@ struct AbcPass : public Pass {
log(" NMUX, AOI3, OAI3, AOI4, OAI4.\n");
log(" (The NOT gate is always added to this list automatically.)\n");
log("\n");
- log(" The following aliases can be used to reference common sets of gate types:\n");
+ log(" The following aliases can be used to reference common sets of gate\n");
+ log(" types:\n");
log(" simple: AND OR XOR MUX\n");
log(" cmos2: NAND NOR\n");
log(" cmos3: NAND NOR AOI3 OAI3\n");
@@ -1576,8 +1577,8 @@ struct AbcPass : public Pass {
log("\n");
log(" -dress\n");
log(" run the 'dress' command after all other ABC commands. This aims to\n");
- log(" preserve naming by an equivalence check between the original and post-ABC\n");
- log(" netlists (experimental).\n");
+ log(" preserve naming by an equivalence check between the original and\n");
+ log(" post-ABC netlists (experimental).\n");
log("\n");
log("When no target cell library is specified the Yosys standard cell library is\n");
log("loaded into ABC before the ABC script is executed.\n");