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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 08:52:14 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 08:52:14 -0700 |
| commit | ba8ccbdea88fe432187e2481a8525cc1c53b4cf4 (patch) | |
| tree | ce3c29d03229cfb18392f2ddc835ce66056aeee4 /passes/techmap/abc.cc | |
| parent | a1a04ea79c4d006baa7204ba5ca77870f45aa633 (diff) | |
| parent | 5fb27c071bb072644dbb38cf8a516628c2afe15b (diff) | |
| download | yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.gz yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.tar.bz2 yosys-ba8ccbdea88fe432187e2481a8525cc1c53b4cf4.zip | |
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 15e79f9d1..65c7d1bb8 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1172,8 +1172,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin continue; } } - - cell_stats[RTLIL::unescape_id(c->type)]++; + else + cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\_const0_" || c->type == "\\_const1_") { RTLIL::SigSig conn; |