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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-06 15:41:13 +0200 |
| commit | d187be39d608966f53d6c2ba4d45de94a584d476 (patch) | |
| tree | 30b9820eddba4341c7270d5b255758967ed7eaf0 /passes/techmap/abc.cc | |
| parent | 5c2c0b4bb2ade51396da3acbcce0d5916fb1c7d6 (diff) | |
| parent | 20268d12a51e157effc209de5613f0ac8308a61f (diff) | |
| download | yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.gz yosys-d187be39d608966f53d6c2ba4d45de94a584d476.tar.bz2 yosys-d187be39d608966f53d6c2ba4d45de94a584d476.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 547115459..5b19d84fb 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -330,20 +330,33 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr) { std::string abc_sname = abc_name.substr(1); - if (abc_sname.substr(0, 5) == "ys__n") { - bool inv = abc_sname.back() == 'v'; - if (inv) abc_sname.pop_back(); + bool isnew = false; + if (abc_sname.substr(0, 4) == "new_") + { + abc_sname.erase(0, 4); + isnew = true; + } + if (abc_sname.substr(0, 5) == "ys__n") + { abc_sname.erase(0, 5); - if (abc_sname.find_last_not_of("012345689") == std::string::npos) { + if (std::isdigit(abc_sname.at(0))) + { int sid = std::stoi(abc_sname); - for (auto sig : signal_list) { - if (sig.id == sid && sig.bit.wire != nullptr) { + size_t postfix_start = abc_sname.find_first_not_of("0123456789"); + std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : ""; + + if (sid < GetSize(signal_list)) + { + auto sig = signal_list.at(sid); + if (sig.bit.wire != nullptr) + { std::stringstream sstr; sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1); if (sig.bit.wire->width != 1) sstr << "[" << sig.bit.offset << "]"; - if (inv) - sstr << "_inv"; + if (isnew) + sstr << "_new"; + sstr << postfix; if (orig_wire != nullptr) *orig_wire = sig.bit.wire; return sstr.str(); |