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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 10:46:06 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 10:46:06 -0800 |
| commit | 1f7893bd8c8d88f2a84b9bcba67acf43cee0430f (patch) | |
| tree | 0ff5005f2c08208262950876934216413cfd29dc /passes/techmap/abc9.cc | |
| parent | ccc83d99bafc74f7ec62111bf61d962ca0a0771d (diff) | |
| download | yosys-1f7893bd8c8d88f2a84b9bcba67acf43cee0430f.tar.gz yosys-1f7893bd8c8d88f2a84b9bcba67acf43cee0430f.tar.bz2 yosys-1f7893bd8c8d88f2a84b9bcba67acf43cee0430f.zip | |
abc9: fix memory leak
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8cb34e523..3fc6ed2c2 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -416,13 +416,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip dict<IdString, bool> abc9_box; vector<RTLIL::Cell*> boxes; - for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { - auto cell = it->second; + for (auto cell : module->cells().to_vector()) { if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) { - it = module->cells_.erase(it); + module->remove(cell); continue; } - ++it; RTLIL::Module* box_module = design->module(cell->type); auto jt = abc9_box.find(cell->type); if (jt == abc9_box.end()) |