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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-01 23:43:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-01 23:43:28 -0800 |
| commit | 6398b7c17c406a502d157d69011b9acb460848ea (patch) | |
| tree | 1d6a03d96c7f8f17ff96c658092412f913c75c1e /passes/techmap/abc9.cc | |
| parent | 1d87488795e4f898e2fcf6a71259a3972dbe7819 (diff) | |
| download | yosys-6398b7c17c406a502d157d69011b9acb460848ea.tar.gz yosys-6398b7c17c406a502d157d69011b9acb460848ea.tar.bz2 yosys-6398b7c17c406a502d157d69011b9acb460848ea.zip | |
Cleanup
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 193103747..5a9cbc245 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1098,7 +1098,7 @@ struct Abc9Pass : public Pass { pool<Wire*> clocks; std::string target = delay_target; - for (auto cell : module->selected_cells()) { + for (auto cell : module->cells()) { auto inst_module = design->module(cell->type); if (!inst_module || !inst_module->attributes.count("\\abc9_flop")) continue; @@ -1119,7 +1119,6 @@ struct Abc9Pass : public Pass { } } - Wire *abc9_control_wire = module->wire(stringf("%s.$abc9_control", cell->name.c_str())); if (abc9_control_wire == NULL) log_error("'%s$abc9_control' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); @@ -1127,7 +1126,7 @@ struct Abc9Pass : public Pass { ctrldomain_t key(cell->type, abc9_control); auto r = mergeability_class.emplace(key, mergeability_class.size() + 1); - auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second)); + auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second)); log_assert(r2.second); } |