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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 09:43:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 09:43:57 -0800 |
| commit | 808b388e34f3cededd450de35555476874cf2799 (patch) | |
| tree | 4e74cdb031ce90d0c5978cd631644b67a2ea1689 /passes/techmap/abc9.cc | |
| parent | 9f3cb981d7c0767f40febf0b32e0a19c28d8e6a0 (diff) | |
| download | yosys-808b388e34f3cededd450de35555476874cf2799.tar.gz yosys-808b388e34f3cededd450de35555476874cf2799.tar.bz2 yosys-808b388e34f3cededd450de35555476874cf2799.zip | |
abc9: log which module is being operated on
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2ded1c162..2e3df773e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -276,9 +276,11 @@ struct Abc9Pass : public ScriptPass run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); - log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n", + + log("Extracted %d AND gates and %d wires from module `%s' to a netlist network with %d inputs and %d outputs.\n", active_design->scratchpad_get_int("write_xaiger.num_ands"), active_design->scratchpad_get_int("write_xaiger.num_wires"), + log_id(mod), active_design->scratchpad_get_int("write_xaiger.num_inputs"), num_outputs); if (num_outputs) { |