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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-16 14:26:58 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-16 14:26:58 +0200 |
| commit | 958be89c47ae4f11b5de07bc026bc2202e2ebc97 (patch) | |
| tree | 82ea78f26a4deb79d3dc08c57638533c434764ca /passes/techmap/abc9.cc | |
| parent | 40c40d9f5d87e1f88d1dec767173d499a3e3c216 (diff) | |
| parent | 72eacdb9f80e24aa2182dbf567d6fcbe2a5bfaba (diff) | |
| download | yosys-958be89c47ae4f11b5de07bc026bc2202e2ebc97.tar.gz yosys-958be89c47ae4f11b5de07bc026bc2202e2ebc97.tar.bz2 yosys-958be89c47ae4f11b5de07bc026bc2202e2ebc97.zip | |
Merge pull request #1302 from mmicko/dfflibmap_regression
DFFLIBMAP pass regression fix
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 752535f34..c3c8f879f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -628,7 +628,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx; continue; } - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats[c->type]++; RTLIL::Cell *existing_cell = nullptr; if (c->type == ID($lut)) { |