diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:40:40 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-14 11:40:40 -0800 |
| commit | 9fa0e03cc90548d0817346d0fcd72473b7d489ae (patch) | |
| tree | 7908b1fb233a8ec4c6b99a632c768b1f93dc3387 /passes/techmap/abc9.cc | |
| parent | 9fbeb57bbdb98265b541d7a62213e83de63c8a1a (diff) | |
| parent | f63f76c372e8003f60565ee109d38ae1797d7e89 (diff) | |
| download | yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.tar.gz yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.tar.bz2 yosys-9fa0e03cc90548d0817346d0fcd72473b7d489ae.zip | |
Merge pull request #1632 from YosysHQ/eddie/fix1630
read_aiger: uniquify wires with $aiger<autoidx> prefix
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8a6195741..1f6cdaa22 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); log_assert(!design->module(ID($__abc9__))); { - AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, /*buffer.c_str()*/ "" /* map_filename */, true /* wideports */); + AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); reader.parse_xaiger(); } ifs.close(); @@ -472,16 +472,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) - driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); + driver_name = stringf("$lut%s", a_bit.wire->name.c_str()); else - driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); + driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset); driver_lut = mapped_mod->cell(driver_name); } if (!driver_lut) { // If a driver couldn't be found (could be from PI or box CI) // then implement using a LUT - cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), + cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); |