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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:17:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:17:03 -0800 |
| commit | c4ec42ac38bd5678d9f3018d3921a3f0f4239986 (patch) | |
| tree | 85b31a3d78ba34a56357f698f6e88ab6352ba350 /passes/techmap/abc9.cc | |
| parent | 5a30e3ac3ba6435ebf9db0f8acfba61e9ee73ad7 (diff) | |
| download | yosys-c4ec42ac38bd5678d9f3018d3921a3f0f4239986.tar.gz yosys-c4ec42ac38bd5678d9f3018d3921a3f0f4239986.tar.bz2 yosys-c4ec42ac38bd5678d9f3018d3921a3f0f4239986.zip | |
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
Since they should be captured downwards from the owning flop
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8d4ff4025..4b6ec6e11 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1165,7 +1165,7 @@ struct Abc9Pass : public Pass { for (auto bit : cell_to_bit_up[cell]) for (auto c : bit_to_cell_up[bit]) - if (unassigned_cells.count(c)) { + if (unassigned_cells.count(c) && !c->type.in("$__ABC9_FF_", "$__ABC9_ASYNC_")) { unassigned_cells.erase(c); next_expand_queue_up.insert(c); assigned_cells[key].insert(c->name); |