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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 16:29:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 16:29:08 -0800 |
| commit | 88b9c8d46ddac513831dc79d370f8abb23ab68fc (patch) | |
| tree | 11888a33ddd94b242200edbccf596f6f06d08765 /passes/techmap/abc9_map.cc | |
| parent | dbffbeef5c2df2345c786e195d2006d7bb23578a (diff) | |
| download | yosys-88b9c8d46ddac513831dc79d370f8abb23ab68fc.tar.gz yosys-88b9c8d46ddac513831dc79d370f8abb23ab68fc.tar.bz2 yosys-88b9c8d46ddac513831dc79d370f8abb23ab68fc.zip | |
Restore count_outputs, move process check to abc
Diffstat (limited to 'passes/techmap/abc9_map.cc')
| -rw-r--r-- | passes/techmap/abc9_map.cc | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc index 7d53db5ea..83f90a762 100644 --- a/passes/techmap/abc9_map.cc +++ b/passes/techmap/abc9_map.cc @@ -268,15 +268,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip log_push(); - // FIXME: - /*int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs"); + int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs"); log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n", design->scratchpad_get_int("write_xaiger.num_ands"), design->scratchpad_get_int("write_xaiger.num_wires"), design->scratchpad_get_int("write_xaiger.num_inputs"), count_outputs); - if (count_outputs > 0)*/ { + if (count_outputs > 0) { std::string buffer; std::ifstream ifs; #if 0 @@ -965,13 +964,8 @@ struct Abc9MapPass : public Pass { CellTypes ct(design); for (auto module : design->selected_modules()) { - if (module->attributes.count(ID(abc9_box_id))) - continue; - - if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes.\n", log_id(module)); - continue; - } + if (module->processes.size() > 0) + log_error("Module '%s' has processes!\n", log_id(module)); assign_map.set(module); |