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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 16:33:41 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 16:33:41 -0800 |
| commit | 485e08e4363f2aa93204f8bcc6c1ff5243936ea6 (patch) | |
| tree | 0e698a1b061eb39f6b2fc92cc6795e28151e619f /passes/techmap/abc9_ops.cc | |
| parent | 48984a7605dc04463329263c3ada4ee2b42cbae7 (diff) | |
| download | yosys-485e08e4363f2aa93204f8bcc6c1ff5243936ea6.tar.gz yosys-485e08e4363f2aa93204f8bcc6c1ff5243936ea6.tar.bz2 yosys-485e08e4363f2aa93204f8bcc6c1ff5243936ea6.zip | |
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4d05b5afb..fd2759ae5 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -117,7 +117,7 @@ void check(RTLIL::Design *design) if (wire->port_output) num_outputs++; } if (num_outputs != 1) - log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs); + log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs); } } } @@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) log_assert(cell); RTLIL::Module* box_module = design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc9_box_id")) + if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop"))) continue; cell->attributes["\\abc9_box_seq"] = box_count++; |