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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 11:46:56 -0800 |
| commit | 53a99ade9cbab883de5d1dcc30ad89d75266df7f (patch) | |
| tree | 17808f6ffdfdd90c44a56aaddf626d5884a821a3 /passes/techmap/abc9_ops.cc | |
| parent | 531fddf797a79b46df3e462112ca68ff50e6a18e (diff) | |
| parent | 61ffd2d1996befd8c27c4f36f07567824bd7605e (diff) | |
| download | yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.gz yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.tar.bz2 yosys-53a99ade9cbab883de5d1dcc30ad89d75266df7f.zip | |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index c7236486f..cc82a72cf 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -488,16 +488,16 @@ void reintegrate(RTLIL::Module *module) // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) - driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); + driver_name = stringf("$lut%s", a_bit.wire->name.c_str()); else - driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); + driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset); driver_lut = mapped_mod->cell(driver_name); } if (!driver_lut) { // If a driver couldn't be found (could be from PI or box CI) // then implement using a LUT - RTLIL::Cell *cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), + RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::Const::from_string("01")); |