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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 14:59:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 14:59:55 -0800 |
| commit | a819656972dd44c479422fa688874926d6239a95 (patch) | |
| tree | d921a90e8175571e3f5da4f25791bd1ede3007f0 /passes/techmap/abc9_ops.cc | |
| parent | 559f3379e852f304a0255afcc37714b9d0da59d9 (diff) | |
| download | yosys-a819656972dd44c479422fa688874926d6239a95.tar.gz yosys-a819656972dd44c479422fa688874926d6239a95.tar.bz2 yosys-a819656972dd44c479422fa688874926d6239a95.zip | |
WIP
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index bcf622dba..632f2bc8a 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -386,8 +386,6 @@ void prep_holes(RTLIL::Module *module) } } - // NB: Assume box_module->ports are sorted alphabetically - // (as RTLIL::Module::fixup_ports() would do) for (const auto &port_name : box_ports.at(cell->type)) { RTLIL::Wire *w = box_module->wire(port_name); log_assert(w); |