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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 18:56:06 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 18:56:06 -0800 |
| commit | f180dba753c9f4bfb3b89575b0d224c73a1e8897 (patch) | |
| tree | 5ad4c18069bbfd3167e9ee3b1b0368b033fc05de /passes/techmap/abc9_ops.cc | |
| parent | 48aec34e0dbb6918e38ef2b80cdbbd8bb992d0f5 (diff) | |
| download | yosys-f180dba753c9f4bfb3b89575b0d224c73a1e8897.tar.gz yosys-f180dba753c9f4bfb3b89575b0d224c73a1e8897.tar.bz2 yosys-f180dba753c9f4bfb3b89575b0d224c73a1e8897.zip | |
abc9_ops: -prep_xaiger to skip (* keep *) cells
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 750f36ceb..40622ece7 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -165,6 +165,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff) for (auto cell : module->cells()) { if (cell->type == "$__ABC9_FF_") continue; + if (cell->has_keep_attr()) + continue; auto inst_module = module->design->module(cell->type); bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id"); |