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authorEddie Hung <eddie@fpgeh.com>2019-08-15 10:25:54 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-15 10:25:54 -0700
commit02dead2e60e802986ac80137667e399d45233cdc (patch)
tree13dc1fa37096c7c83159b6403ff703e213be197d /passes/techmap/dff2dffs.cc
parent467c34eff05bd62fd64c35f07fe140f33edf4511 (diff)
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ID(\\.*) -> ID(.*)
Diffstat (limited to 'passes/techmap/dff2dffs.cc')
-rw-r--r--passes/techmap/dff2dffs.cc18
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index f31bfeef9..f74001b77 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -72,16 +72,16 @@ struct Dff2dffsPass : public Pass {
if (cell->type != ID($_MUX_))
continue;
- SigBit bit_a = sigmap(cell->getPort(ID(\\A)));
- SigBit bit_b = sigmap(cell->getPort(ID(\\B)));
+ SigBit bit_a = sigmap(cell->getPort(ID(A)));
+ SigBit bit_b = sigmap(cell->getPort(ID(B)));
if (bit_a.wire == nullptr || bit_b.wire == nullptr)
- sr_muxes[sigmap(cell->getPort(ID(\\Y)))] = cell;
+ sr_muxes[sigmap(cell->getPort(ID(Y)))] = cell;
}
for (auto cell : ff_cells)
{
- SigSpec sig_d = cell->getPort(ID(\\D));
+ SigSpec sig_d = cell->getPort(ID(D));
if (GetSize(sig_d) < 1)
continue;
@@ -92,9 +92,9 @@ struct Dff2dffsPass : public Pass {
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
- SigBit bit_a = sigmap(mux_cell->getPort(ID(\\A)));
- SigBit bit_b = sigmap(mux_cell->getPort(ID(\\B)));
- SigBit bit_s = sigmap(mux_cell->getPort(ID(\\S)));
+ SigBit bit_a = sigmap(mux_cell->getPort(ID(A)));
+ SigBit bit_b = sigmap(mux_cell->getPort(ID(B)));
+ SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
@@ -132,8 +132,8 @@ struct Dff2dffsPass : public Pass {
else cell->type = ID($__DFFS_PP0_);
}
}
- cell->setPort(ID(\\R), sr_sig);
- cell->setPort(ID(\\D), bit_d);
+ cell->setPort(ID(R), sr_sig);
+ cell->setPort(ID(D), bit_d);
}
}
}