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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-23 17:25:46 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-23 18:24:53 +0200 |
| commit | 88e7f90663f440b24d97a65804ee23b1d82dbed7 (patch) | |
| tree | fc1d103152be86dbb4fc83b5566b17e9b1490445 /passes/techmap/dff2dffs.cc | |
| parent | e71d82759029470663037eb299791d03fef83287 (diff) | |
| download | yosys-88e7f90663f440b24d97a65804ee23b1d82dbed7.tar.gz yosys-88e7f90663f440b24d97a65804ee23b1d82dbed7.tar.bz2 yosys-88e7f90663f440b24d97a65804ee23b1d82dbed7.zip | |
Update dff2dffe, dff2dffs, zinit to new FF types.
Diffstat (limited to 'passes/techmap/dff2dffs.cc')
| -rw-r--r-- | passes/techmap/dff2dffs.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc index 1cb923445..6c2cca4bc 100644 --- a/passes/techmap/dff2dffs.cc +++ b/passes/techmap/dff2dffs.cc @@ -31,7 +31,7 @@ struct Dff2dffsPass : public Pass { log("\n"); log(" dff2dffs [options] [selection]\n"); log("\n"); - log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n"); + log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n"); log("dff2dffe for SR over CE priority.\n"); log("\n"); log(" -match-init\n"); @@ -138,21 +138,21 @@ struct Dff2dffsPass : public Pass { if (sr_val == State::S1) { if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($__DFFS_NN1_); - else cell->type = ID($__DFFS_NP1_); + if (invert_sr) cell->type = ID($_SDFF_NN1_); + else cell->type = ID($_SDFF_NP1_); } else { log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($__DFFS_PN1_); - else cell->type = ID($__DFFS_PP1_); + if (invert_sr) cell->type = ID($_SDFF_PN1_); + else cell->type = ID($_SDFF_PP1_); } } else { if (cell->type == ID($_DFF_N_)) { - if (invert_sr) cell->type = ID($__DFFS_NN0_); - else cell->type = ID($__DFFS_NP0_); + if (invert_sr) cell->type = ID($_SDFF_NN0_); + else cell->type = ID($_SDFF_NP0_); } else { log_assert(cell->type == ID($_DFF_P_)); - if (invert_sr) cell->type = ID($__DFFS_PN0_); - else cell->type = ID($__DFFS_PP0_); + if (invert_sr) cell->type = ID($_SDFF_PN0_); + else cell->type = ID($_SDFF_PP0_); } } cell->setPort(ID::R, sr_sig); |