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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 11:57:52 -0700 |
commit | d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch) | |
tree | aceb37b755f6b112e754bbdd50f0a4a6a6ee111d /passes/techmap/dffinit.cc | |
parent | 297a9802122817e143b1e4b87fd0d4e357606a72 (diff) | |
parent | 3f4886e7a3ff14578b9c6d614efd360478e5886e (diff) | |
download | yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.gz yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.tar.bz2 yosys-d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7.zip |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'passes/techmap/dffinit.cc')
-rw-r--r-- | passes/techmap/dffinit.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 0ad33dc0e..cf9301442 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -99,8 +99,8 @@ struct DffinitPass : public Pass { pool<SigBit> used_bits; for (auto wire : module->selected_wires()) { - if (wire->attributes.count("\\init")) { - Const value = wire->attributes.at("\\init"); + if (wire->attributes.count(ID(init))) { + Const value = wire->attributes.at(ID(init)); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) if (value[i] != State::Sx) init_bits[sigmap(SigBit(wire, i))] = value[i]; @@ -161,8 +161,8 @@ struct DffinitPass : public Pass { } for (auto wire : module->selected_wires()) - if (wire->attributes.count("\\init")) { - Const &value = wire->attributes.at("\\init"); + if (wire->attributes.count(ID(init))) { + Const &value = wire->attributes.at(ID(init)); bool do_cleanup = true; for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { SigBit bit = sigmap(SigBit(wire, i)); @@ -173,7 +173,7 @@ struct DffinitPass : public Pass { } if (do_cleanup) { log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire)); - wire->attributes.erase("\\init"); + wire->attributes.erase(ID(init)); } } } |