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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
| commit | f7a9769c140f6a56e51d7384dfd8e76bf2aef66d (patch) | |
| tree | 4be49b8b30a03ac7d4deafaa7318de275d5c3a7f /passes/techmap/dffinit.cc | |
| parent | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (diff) | |
| parent | a91ea6612a73568782c80bd12ce2875353e2b5c5 (diff) | |
| download | yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.gz yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.bz2 yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/techmap/dffinit.cc')
| -rw-r--r-- | passes/techmap/dffinit.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 48390488e..0ad33dc0e 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -102,7 +102,8 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) - init_bits[sigmap(SigBit(wire, i))] = value[i]; + if (value[i] != State::Sx) + init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) for (auto bit : sigmap(wire)) |