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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
| commit | 307dc55d65f9b9c07c10f6043ce0f165aac3852e (patch) | |
| tree | 3c48790ce444bc2de95d20b01181f6d871e53fbb /passes/techmap/dfflibmap.cc | |
| parent | 85303334396904edfa0d77852b77c64870468f79 (diff) | |
| parent | 8a66bd30c67c753149a195b951a3191d8e5e3304 (diff) | |
| download | yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.gz yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.bz2 yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.zip | |
Merge branch 'ChipScan-master'
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index c8104fb7e..4cb1489a8 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -478,11 +478,15 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare auto cell_type = cell->type; auto cell_name = cell->name; auto cell_connections = cell->connections(); + std::string src = cell->get_src_attribute(); + module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name); + new_cell->set_src_attribute(src); + bool has_q = false, has_qn = false; for (auto &port : cm.ports) { if (port.second == 'Q') has_q = true; |