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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:13:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-02 07:13:33 -0700 |
| commit | 37f42fe102e329793b884a47321423062eedfce7 (patch) | |
| tree | 42cca1494ce7d806e8a638fe56bc8acd13733a21 /passes/techmap/flowmap.cc | |
| parent | 347774945972dc71910a3e38c9ec678f74f97d03 (diff) | |
| parent | 348e8923148f1cc1bfb87bb71b7566d4bc111704 (diff) | |
| download | yosys-37f42fe102e329793b884a47321423062eedfce7.tar.gz yosys-37f42fe102e329793b884a47321423062eedfce7.tar.bz2 yosys-37f42fe102e329793b884a47321423062eedfce7.zip | |
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
Diffstat (limited to 'passes/techmap/flowmap.cc')
| -rw-r--r-- | passes/techmap/flowmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index a2ad87f7d..427b72a6a 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1405,7 +1405,7 @@ struct FlowmapWorker RTLIL::SigSpec lut_a, lut_y = node; for (auto input_node : input_nodes) - lut_a.append_bit(input_node); + lut_a.append(input_node); lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); |